// ******************************************************************************
// Copyright     :  Copyright (C) 2019, Hisilicon Technologies Co. Ltd.
// File name     :  stfiq_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Version       :  V100
// Date          :  2018/12/04
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :   2019/10/17 10:06:12 Create file
// ******************************************************************************

#ifndef STFIQ_C_UNION_DEFINE_H
#define STFIQ_C_UNION_DEFINE_H

/* Define the union csr_stfiq_mode_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_tpmem_timing_ctrl : 8;   /* [7:0] */
        u32 csr_stfiq_spmem_timing_ctrl : 8;   /* [15:8] */
        u32 csr_stfiq_tpmem_power_ctrl : 3;    /* [18:16] */
        u32 csr_stfiq_spmem_power_ctrl : 3;    /* [21:19] */
        u32 csr_stfiq_mem_init_start : 1;      /* [22] */
        u32 csr_stfiq_mem_ecc_bypass : 1;      /* [23] */
        u32 csr_stfiq_mem_ecc_req : 2;         /* [25:24] */
        u32 csr_stfiq_cntx_sf_watchdog_en : 1; /* [26] */
        u32 rsv_0 : 5;                         /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_mode_u;

/* Define the union csr_stfiq_imsg_bm_ini_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_bm_ini_start : 1;             /* [0] */
        u32 imsg_bm_ini_depth : 8;             /* [8:1] */
        u32 imsg_bm_time_out_interval_cfg : 1; /* [9] */
        u32 rsv_1 : 22;                        /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_bm_ini_u;

/* Define the union csr_stfiq_imsg_bm_time_out_interval_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_bm_time_out_interval : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_bm_time_out_interval_u;

/* Define the union csr_stfiq_imsg_bm_infor_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_bm_ini_busy : 1; /* [0] */
        u32 imsg_bm_ini_done : 1; /* [1] */
        u32 rsv_2 : 30;           /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_bm_infor_u;

/* Define the union csr_stfiq_imsg_pro_type_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_stf_tmr_pro_typ : 7; /* [6:0] */
        u32 imsg_stl_tmr_pro_typ : 7; /* [13:7] */
        u32 imsg_fcnp_pro_typ : 7;    /* [20:14] */
        u32 imsg_event_pro_typ : 11;  /* [31:21] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_pro_type_u;

/* Define the union csr_stfiq_imsg_source_limit_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_msg_pfhid_limit : 9;              /* [8:0] */
        u32 imsg_msg_pfhid_stl_task_tmr_limit : 8; /* [16:9] */
        u32 rsv_3 : 15;                            /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_source_limit_u;

/* Define the union csr_stfiq_imsg_dbe_psh_cpb_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_dbe_psh_cpb : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_dbe_psh_cpb_u;

/* Define the union csr_stfiq_imsg_tmr_src_define0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_tmr_stl_src : 12; /* [11:0] */
        u32 imsg_tmr_stf_src : 12; /* [23:12] */
        u32 rsv_4 : 8;             /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_tmr_src_define0_u;

/* Define the union csr_stfiq_imsg_event_src_define1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_tsk_src : 12;  /* [11:0] */
        u32 imsg_fcnp_src : 12; /* [23:12] */
        u32 rsv_5 : 8;          /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_event_src_define1_u;

/* Define the union csr_stfiq_close_fq_load_balance_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 close_fq_load_balance : 1; /* [0] */
        u32 rsv_6 : 31;                /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_close_fq_load_balance_u;

/* Define the union csr_stfiq_fq_qpc_rsp_fifo_aful_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_fq0_qpc_rsp_aful : 6; /* [5:0] */
        u32 stfiq_fq1_qpc_rsp_aful : 6; /* [11:6] */
        u32 rsv_7 : 20;                 /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_fq_qpc_rsp_fifo_aful_u;

/* Define the union csr_stfiq_fq_qpc_rsp_fifo_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_fq0_qpc_rsp_cnt : 6; /* [5:0] */
        u32 stfiq_fq1_qpc_rsp_cnt : 6; /* [11:6] */
        u32 rsv_8 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_fq_qpc_rsp_fifo_cnt_u;

/* Define the union csr_stfiq_ritf_perx_io_last_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 perx_io_last_flag_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_perx_io_last_num_u;

/* Define the union csr_stfiq_ritf_perx_io_first_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 perx_io_first_flag_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_perx_io_first_num_u;

/* Define the union csr_stfiq_ritf_ipsutx_io_last_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ipsutx_io_last_flag_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_ipsutx_io_last_num_u;

/* Define the union csr_stfiq_ritf_ipsutx_io_first_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ipsutx_io_first_flag_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_ipsutx_io_first_num_u;

/* Define the union csr_stfiq_ritf_io_rsp_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ritf_io_rsp_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_io_rsp_num_u;

/* Define the union csr_stfiq_wrr_weight_enq0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_wrr_weight_stffq_lb : 8;  /* [7:0] */
        u32 stfiq_wrr_weight_oq_lb : 8;     /* [15:8] */
        u32 stfiq_wrr_weight_icdq : 8;      /* [23:16] */
        u32 stfiq_wrr_weight_stlfq_dsp : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_wrr_weight_enq0_u;

/* Define the union csr_stfiq_wrr_weight_enq1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_wrr_weight_stliq_ret : 8; /* [7:0] */
        u32 rsv_9 : 24;                     /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_wrr_weight_enq1_u;

/* Define the union csr_stfiq_flb_update_pd_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 flb_update_pd_en : 1;  /* [0] */
        u32 flb_update_epd_en : 1; /* [1] */
        u32 rsv_10 : 30;           /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_flb_update_pd_en_u;

/* Define the union csr_stfiq_errpkt_drop_en0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 errpkt_drop_en0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_errpkt_drop_en0_u;

/* Define the union csr_stfiq_errpkt_drop_en1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 errpkt_drop_en1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_errpkt_drop_en1_u;

/* Define the union csr_stfiq_errpkt_drop_en2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 errpkt_drop_en2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_errpkt_drop_en2_u;

/* Define the union csr_stfiq_errpkt_drop_en3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 errpkt_drop_en3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_errpkt_drop_en3_u;

/* Define the union csr_stfiq_wrr_weight_enq2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_wrr_weight_qry : 8; /* [7:0] */
        u32 stfiq_wrr_weight_enq : 8; /* [15:8] */
        u32 rsv_11 : 16;              /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_wrr_weight_enq2_u;

/* Define the union csr_stfiq_imsg_msg_fifo_af_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_dbe_aful : 9;  /* [8:0] */
        u32 fq0_timer_aful : 9; /* [17:9] */
        u32 fq1_timer_aful : 9; /* [26:18] */
        u32 rsv_12 : 5;         /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_msg_fifo_af_u;

/* Define the union csr_stfiq_imsg_stl_stf_msg_af_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stlmsg_aful : 6; /* [5:0] */
        u32 stfmsg_aful : 6; /* [11:6] */
        u32 rsv_13 : 20;     /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_stl_stf_msg_af_u;

/* Define the union csr_stfiq_ritf_fifo_aful0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pe_event_aful : 5;     /* [4:0] */
        u32 fcnp_event_aful : 13;  /* [17:5] */
        u32 perx_event_aful : 6;   /* [23:18] */
        u32 ipsutx_event_aful : 6; /* [29:24] */
        u32 rsv_14 : 2;            /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_fifo_aful0_u;

/* Define the union csr_stfiq_ritf_fifo_aful1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 taskid_order_aful : 15; /* [14:0] */
        u32 rsv_15 : 17;            /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_fifo_aful1_u;

/* Define the union csr_stfiq_iarb_fifo_aful0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stor_icdq_infor_aful : 7;       /* [6:0] */
        u32 stor_stffq0_flb_infor_aful : 7; /* [13:7] */
        u32 stor_stffq1_flb_infor_aful : 7; /* [20:14] */
        u32 stor_oq_olb_infor_aful : 7;     /* [27:21] */
        u32 rsv_16 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iarb_fifo_aful0_u;

/* Define the union csr_stfiq_iarb_fifo_aful1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stor_stliq_ret_infor_aful : 7;  /* [6:0] */
        u32 stor_stlfq_dsp_infor_aful : 7;  /* [13:7] */
        u32 stor_stffq0_qry_infor_aful : 7; /* [20:14] */
        u32 stor_stffq1_qry_infor_aful : 7; /* [27:21] */
        u32 rsv_17 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iarb_fifo_aful1_u;

/* Define the union csr_stfiq_iarb_fifo_aful2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stor_pd_infor_aful : 7; /* [6:0] */
        u32 rsv_18 : 25;            /* [31:7] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iarb_fifo_aful2_u;

/* Define the union csr_stfiq_imsg_msg_fifo_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_dbe_cnt : 9;  /* [8:0] */
        u32 fq0_timer_cnt : 9; /* [17:9] */
        u32 fq1_timer_cnt : 9; /* [26:18] */
        u32 rsv_19 : 5;        /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_msg_fifo_cnt_u;

/* Define the union csr_stfiq_imsg_stl_stf_msg_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stlmsg_cnt : 6;  /* [5:0] */
        u32 stfmsg_cnt0 : 6; /* [11:6] */
        u32 stfmsg_cnt1 : 6; /* [17:12] */
        u32 rsv_20 : 14;     /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_imsg_stl_stf_msg_cnt_u;

/* Define the union csr_stfiq_ritf_fifo_cnt0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pe_event_cnt : 5;     /* [4:0] */
        u32 fcnp_event_cnt : 13;  /* [17:5] */
        u32 perx_event_cnt : 6;   /* [23:18] */
        u32 ipsutx_event_cnt : 6; /* [29:24] */
        u32 rsv_21 : 2;           /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_fifo_cnt0_u;

/* Define the union csr_stfiq_ritf_fifo_cnt1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 taskid_order_cnt : 15; /* [14:0] */
        u32 rsv_22 : 17;           /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ritf_fifo_cnt1_u;

/* Define the union csr_stfiq_iarb_fifo_cnt0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stor_icdq_infor_cnt : 7;       /* [6:0] */
        u32 stor_stffq0_flb_infor_cnt : 7; /* [13:7] */
        u32 stor_stffq1_flb_infor_cnt : 7; /* [20:14] */
        u32 stor_oq_olb_infor_cnt : 7;     /* [27:21] */
        u32 rsv_23 : 4;                    /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iarb_fifo_cnt0_u;

/* Define the union csr_stfiq_iarb_fifo_cnt1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stor_stliq_ret_infor_cnt : 7;  /* [6:0] */
        u32 stor_stlfq_dsp_infor_cnt : 7;  /* [13:7] */
        u32 stor_stffq0_qry_infor_cnt : 7; /* [20:14] */
        u32 stor_stffq1_qry_infor_cnt : 7; /* [27:21] */
        u32 rsv_24 : 4;                    /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iarb_fifo_cnt1_u;

/* Define the union csr_stfiq_iarb_fifo_cnt2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stor_pd_infor_cnt : 7; /* [6:0] */
        u32 rsv_25 : 25;           /* [31:7] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iarb_fifo_cnt2_u;

/* Define the union csr_stfiq_mem_init_done_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 mem_init_done : 1; /* [0] */
        u32 rsv_26 : 31;       /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_mem_init_done_u;

/* Define the union csr_stfiq_int_vector_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cpi_int_index : 24; /* [23:0] */
        u32 rsv_27 : 3;         /* [26:24] */
        u32 enable : 1;         /* [27] */
        u32 int_issue : 1;      /* [28] */
        u32 rsv_28 : 3;         /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int_vector_u;

/* Define the union csr_stfiq_int_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 int_data : 16;          /* [15:0] */
        u32 program_csr_id_ro : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int_u;

/* Define the union csr_stfiq_int_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 int_en : 16;         /* [15:0] */
        u32 program_csr_id : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int_en_u;

/* Define the union csr_stfiq_int0_sticky_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 imsg_bm_time_out_rpt : 1; /* [0] */
        u32 int_insrt0 : 1;           /* [1] */
        u32 stfiq_int0_sticky : 30;   /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int0_sticky_u;

/* Define the union csr_stfiq_int1_sticky_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_fifo_overflow0 : 1; /* [0] */
        u32 int_insrt10 : 1;          /* [1] */
        u32 stfiq_int1_sticky0 : 30;  /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int1_sticky_u;

/* Define the union csr_stfiq_int2_sticky_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_fifo_underflow0 : 1; /* [0] */
        u32 int_insrt20 : 1;           /* [1] */
        u32 stfiq_int2_sticky0 : 30;   /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int2_sticky_u;

/* Define the union csr_stfiq_int3_sticky_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_ram_ecc_cerr : 1; /* [0] */
        u32 int_insrt3 : 1;         /* [1] */
        u32 stfiq_int3_sticky : 30; /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int3_sticky_u;

/* Define the union csr_stfiq_int4_sticky_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_ram_ecc_ucerr : 1; /* [0] */
        u32 int_insrt4 : 1;          /* [1] */
        u32 stfiq_int4_sticky : 30;  /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_int4_sticky_u;

/* Define the union csr_stfiq_indrect_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_ctrl : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_ctrl_u;

/* Define the union csr_stfiq_indrect_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_timeout : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_timeout_u;

/* Define the union csr_stfiq_indrect_dat0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_data0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_dat0_u;

/* Define the union csr_stfiq_indrect_dat1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_data1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_dat1_u;

/* Define the union csr_stfiq_indrect_dat2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_data2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_dat2_u;

/* Define the union csr_stfiq_indrect_dat3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_data3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_dat3_u;

/* Define the union csr_stfiq_indrect_dat4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_data4 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_dat4_u;

/* Define the union csr_stfiq_indrect_dat5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_data5 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_dat5_u;

/* Define the union csr_stfiq_indrect_dat6_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_indrect_data6 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_indrect_dat6_u;

/* Define the union csr_stfiq_prefetch_req_cnt0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_prefetch_req_inc0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_prefetch_req_cnt0_u;

/* Define the union csr_stfiq_prefetch_req_cnt1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_prefetch_req_inc1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_prefetch_req_cnt1_u;

/* Define the union csr_stfiq_prefetch_rsp_cnt0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_prefetch_rsp_cnt0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_prefetch_rsp_cnt0_u;

/* Define the union csr_stfiq_prefetch_rsp_cnt1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_prefetch_rsp_cnt1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_prefetch_rsp_cnt1_u;

/* Define the union csr_stfiq_cnt_db_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_cnt_db_inc : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_cnt_db_u;

/* Define the union csr_stfiq_cnt_tmr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_cnt_tmr_inc : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_cnt_tmr_u;

/* Define the union csr_stfiq_cnt_tsk_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_cnt_tsk_inc : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_cnt_tsk_u;

/* Define the union csr_stfiq_cnt_fcnp_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_cnt_fcnp_inc : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_cnt_fcnp_u;

/* Define the union csr_stfiq_cnt_msg_schedule_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_cnt_msg_schedule_inc : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_cnt_msg_schedule_u;

/* Define the union csr_stfiq_earb_roce_rd_pro_type0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_roce_rd_pro_type0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_earb_roce_rd_pro_type0_u;

/* Define the union csr_stfiq_iqm_fret_err_drop0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 fret_err_drop_en0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iqm_fret_err_drop0_u;

/* Define the union csr_stfiq_iqm_fret_err_drop1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 fret_err_drop_en1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iqm_fret_err_drop1_u;

/* Define the union csr_stfiq_iqm_fret_err_drop2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 fret_err_drop_en2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iqm_fret_err_drop2_u;

/* Define the union csr_stfiq_iqm_fret_err_drop3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 fret_err_drop_en3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_iqm_fret_err_drop3_u;

/* Define the union csr_stfiq_ifp_start_time_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_ifp_start_time_cnt : 8; /* [7:0] */
        u32 rsv_29 : 24;                      /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_ifp_start_time_cnt_u;

/* Define the union csr_stfiq_qry_fifo_aful_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 qry_eop_gain_fifo_af_th : 7; /* [6:0] */
        u32 cntxsf_fifo_af_th : 6;       /* [12:7] */
        u32 rsv_30 : 19;                 /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_qry_fifo_aful_u;

/* Define the union csr_stfiq_qry_fifo_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 qry_eop_gain_fifo_fill : 7; /* [6:0] */
        u32 cntxsf_fifo_fill : 6;       /* [12:7] */
        u32 rsv_31 : 19;                /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_qry_fifo_cnt_u;

/* Define the union csr_stfiq_icdq_sqd_bp_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_iqm_cfg_sqd_bp : 8; /* [7:0] */
        u32 rsv_32 : 24;            /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_icdq_sqd_bp_u;

/* Define the union csr_stfiq_latency_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_sample_mode : 1;   /* [0] */
        u32 csr_stfiq_spec_port_en : 1;  /* [1] */
        u32 csr_stfiq_done_clr : 1;      /* [2] */
        u32 rsv_33 : 1;                  /* [3] */
        u32 csr_stfiq_spec_port_num : 4; /* [7:4] */
        u32 csr_stfiq_spec_pptr_typ : 8; /* [15:8] */
        u32 rsv_34 : 16;                 /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_latency_cfg_u;

/* Define the union csr_stfiq_latency_sta_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_sample_done : 1; /* [0] */
        u32 rsv_35 : 31;               /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_latency_sta_u;

/* Define the union csr_stfiq_sample_tmr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfiq_csr_sample_tmr : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_sample_tmr_u;

/* Define the union csr_stfiq_earb_roce_rd_pro_type1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_roce_rd_pro_type1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_earb_roce_rd_pro_type1_u;

/* Define the union csr_stfiq_earb_roce_rd_pro_type2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_roce_rd_pro_type2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_earb_roce_rd_pro_type2_u;

/* Define the union csr_stfiq_earb_roce_rd_pro_type3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_roce_rd_pro_type3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_earb_roce_rd_pro_type3_u;

/* Define the union csr_stfiq_quf_pg_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_quf_pg_cfg : 2; /* [1:0] */
        u32 rsv_36 : 30;              /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_quf_pg_cfg_u;

/* Define the union csr_stfiq_cntx_timout_wattermark_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_cntx_sf_timeout_watermark : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_cntx_timout_wattermark_u;

/* Define the union csr_stfiq_fake_vf_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_stfiq_fake_vf_mask : 12; /* [11:0] */
        u32 rsv_37 : 20;                 /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stfiq_fake_vf_mask_u;

/* Define the union csr_cmd_pkt_ichannel0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cmd_pkt_ichannel0 : 8; /* [7:0] */
        u32 cmd_pkt_ichannel1 : 8; /* [15:8] */
        u32 cmd_pkt_ichannel2 : 8; /* [23:16] */
        u32 cmd_pkt_ichannel3 : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cmd_pkt_ichannel0_u;

/* Define the union csr_cmd_pkt_ichannel1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cmd_pkt_ichannel4 : 8; /* [7:0] */
        u32 cmd_pkt_ichannel5 : 8; /* [15:8] */
        u32 cmd_pkt_ichannel6 : 8; /* [23:16] */
        u32 cmd_pkt_ichannel7 : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cmd_pkt_ichannel1_u;

/* Define the union csr_csr_iqm_cfg_threshold_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_iqm_cfg_threshold0 : 16; /* [15:0] */
        u32 csr_iqm_cfg_threshold1 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_csr_iqm_cfg_threshold_u;

/* Define the union csr_csr_iqm_time_interval_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_iqm_time_interval : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_csr_iqm_time_interval_u;

/* Define the union csr_csr_iqm_time_out_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_iqm_time_out_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_csr_iqm_time_out_cnt_u;

/* Define the union csr_csr_iqm_time_out_queue0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_iqm_time_out_queue0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_csr_iqm_time_out_queue0_u;

/* Define the union csr_csr_iqm_time_out_queue1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_iqm_time_out_queue1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_csr_iqm_time_out_queue1_u;

/* Define the union csr_csr_iqm_time_out_start_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 csr_iqm_time_out_start : 1; /* [0] */
        u32 rsv_38 : 31;                /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_csr_iqm_time_out_start_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_stfiq_mode_u stfiq_mode;                                           /* 0 */
    volatile csr_stfiq_imsg_bm_ini_u stfiq_imsg_bm_ini;                             /* 4 */
    volatile csr_stfiq_imsg_bm_time_out_interval_u stfiq_imsg_bm_time_out_interval; /* 8 */
    volatile csr_stfiq_imsg_bm_infor_u stfiq_imsg_bm_infor;                         /* C */
    volatile csr_stfiq_imsg_pro_type_u stfiq_imsg_pro_type;                         /* 10 */
    volatile csr_stfiq_imsg_source_limit_u stfiq_imsg_source_limit;                 /* 14 */
    volatile csr_stfiq_imsg_dbe_psh_cpb_u stfiq_imsg_dbe_psh_cpb;                   /* 18 */
    volatile csr_stfiq_imsg_tmr_src_define0_u stfiq_imsg_tmr_src_define0;           /* 1C */
    volatile csr_stfiq_imsg_event_src_define1_u stfiq_imsg_event_src_define1;       /* 20 */
    volatile csr_stfiq_close_fq_load_balance_u stfiq_close_fq_load_balance;         /* 24 */
    volatile csr_stfiq_fq_qpc_rsp_fifo_aful_u stfiq_fq_qpc_rsp_fifo_aful;           /* 28 */
    volatile csr_stfiq_fq_qpc_rsp_fifo_cnt_u stfiq_fq_qpc_rsp_fifo_cnt;             /* 2C */
    volatile csr_stfiq_ritf_perx_io_last_num_u stfiq_ritf_perx_io_last_num;         /* 30 */
    volatile csr_stfiq_ritf_perx_io_first_num_u stfiq_ritf_perx_io_first_num;       /* 34 */
    volatile csr_stfiq_ritf_ipsutx_io_last_num_u stfiq_ritf_ipsutx_io_last_num;     /* 38 */
    volatile csr_stfiq_ritf_ipsutx_io_first_num_u stfiq_ritf_ipsutx_io_first_num;   /* 3C */
    volatile csr_stfiq_ritf_io_rsp_num_u stfiq_ritf_io_rsp_num;                     /* 40 */
    volatile csr_stfiq_wrr_weight_enq0_u stfiq_wrr_weight_enq0;                     /* 44 */
    volatile csr_stfiq_wrr_weight_enq1_u stfiq_wrr_weight_enq1;                     /* 48 */
    volatile csr_stfiq_flb_update_pd_en_u stfiq_flb_update_pd_en;                   /* 4C */
    volatile csr_stfiq_errpkt_drop_en0_u stfiq_errpkt_drop_en0;                     /* 50 */
    volatile csr_stfiq_errpkt_drop_en1_u stfiq_errpkt_drop_en1;                     /* 54 */
    volatile csr_stfiq_errpkt_drop_en2_u stfiq_errpkt_drop_en2;                     /* 58 */
    volatile csr_stfiq_errpkt_drop_en3_u stfiq_errpkt_drop_en3;                     /* 5C */
    volatile csr_stfiq_wrr_weight_enq2_u stfiq_wrr_weight_enq2;                     /* 60 */
    volatile csr_stfiq_imsg_msg_fifo_af_u stfiq_imsg_msg_fifo_af;                   /* 64 */
    volatile csr_stfiq_imsg_stl_stf_msg_af_u stfiq_imsg_stl_stf_msg_af;             /* 68 */
    volatile csr_stfiq_ritf_fifo_aful0_u stfiq_ritf_fifo_aful0;                     /* 6C */
    volatile csr_stfiq_ritf_fifo_aful1_u stfiq_ritf_fifo_aful1;                     /* 70 */
    volatile csr_stfiq_iarb_fifo_aful0_u stfiq_iarb_fifo_aful0;                     /* 74 */
    volatile csr_stfiq_iarb_fifo_aful1_u stfiq_iarb_fifo_aful1;                     /* 78 */
    volatile csr_stfiq_iarb_fifo_aful2_u stfiq_iarb_fifo_aful2;                     /* 7C */
    volatile csr_stfiq_imsg_msg_fifo_cnt_u stfiq_imsg_msg_fifo_cnt;                 /* 80 */
    volatile csr_stfiq_imsg_stl_stf_msg_cnt_u stfiq_imsg_stl_stf_msg_cnt;           /* 84 */
    volatile csr_stfiq_ritf_fifo_cnt0_u stfiq_ritf_fifo_cnt0;                       /* 88 */
    volatile csr_stfiq_ritf_fifo_cnt1_u stfiq_ritf_fifo_cnt1;                       /* 8C */
    volatile csr_stfiq_iarb_fifo_cnt0_u stfiq_iarb_fifo_cnt0;                       /* 90 */
    volatile csr_stfiq_iarb_fifo_cnt1_u stfiq_iarb_fifo_cnt1;                       /* 94 */
    volatile csr_stfiq_iarb_fifo_cnt2_u stfiq_iarb_fifo_cnt2;                       /* 98 */
    volatile csr_stfiq_mem_init_done_u stfiq_mem_init_done;                         /* 9C */
    volatile csr_stfiq_int_vector_u stfiq_int_vector;                               /* A0 */
    volatile csr_stfiq_int_u stfiq_int;                                             /* A4 */
    volatile csr_stfiq_int_en_u stfiq_int_en;                                       /* A8 */
    volatile csr_stfiq_int0_sticky_u stfiq_int0_sticky;                             /* AC */
    volatile csr_stfiq_int1_sticky_u stfiq_int1_sticky;                             /* B0 */
    volatile csr_stfiq_int2_sticky_u stfiq_int2_sticky;                             /* C8 */
    volatile csr_stfiq_int3_sticky_u stfiq_int3_sticky;                             /* E0 */
    volatile csr_stfiq_int4_sticky_u stfiq_int4_sticky;                             /* E4 */
    volatile csr_stfiq_indrect_ctrl_u stfiq_indrect_ctrl;                           /* E8 */
    volatile csr_stfiq_indrect_timeout_u stfiq_indrect_timeout;                     /* EC */
    volatile csr_stfiq_indrect_dat0_u stfiq_indrect_dat0;                           /* F0 */
    volatile csr_stfiq_indrect_dat1_u stfiq_indrect_dat1;                           /* F4 */
    volatile csr_stfiq_indrect_dat2_u stfiq_indrect_dat2;                           /* F8 */
    volatile csr_stfiq_indrect_dat3_u stfiq_indrect_dat3;                           /* FC */
    volatile csr_stfiq_indrect_dat4_u stfiq_indrect_dat4;                           /* 100 */
    volatile csr_stfiq_indrect_dat5_u stfiq_indrect_dat5;                           /* 104 */
    volatile csr_stfiq_indrect_dat6_u stfiq_indrect_dat6;                           /* 108 */
    volatile csr_stfiq_prefetch_req_cnt0_u stfiq_prefetch_req_cnt0;                 /* 10C */
    volatile csr_stfiq_prefetch_req_cnt1_u stfiq_prefetch_req_cnt1;                 /* 110 */
    volatile csr_stfiq_prefetch_rsp_cnt0_u stfiq_prefetch_rsp_cnt0;                 /* 114 */
    volatile csr_stfiq_prefetch_rsp_cnt1_u stfiq_prefetch_rsp_cnt1;                 /* 118 */
    volatile csr_stfiq_cnt_db_u stfiq_cnt_db;                                       /* 11C */
    volatile csr_stfiq_cnt_tmr_u stfiq_cnt_tmr;                                     /* 120 */
    volatile csr_stfiq_cnt_tsk_u stfiq_cnt_tsk;                                     /* 124 */
    volatile csr_stfiq_cnt_fcnp_u stfiq_cnt_fcnp;                                   /* 128 */
    volatile csr_stfiq_cnt_msg_schedule_u stfiq_cnt_msg_schedule;                   /* 12C */
    volatile csr_stfiq_earb_roce_rd_pro_type0_u stfiq_earb_roce_rd_pro_type0;       /* 130 */
    volatile csr_stfiq_iqm_fret_err_drop0_u stfiq_iqm_fret_err_drop0;               /* 134 */
    volatile csr_stfiq_iqm_fret_err_drop1_u stfiq_iqm_fret_err_drop1;               /* 138 */
    volatile csr_stfiq_iqm_fret_err_drop2_u stfiq_iqm_fret_err_drop2;               /* 13C */
    volatile csr_stfiq_iqm_fret_err_drop3_u stfiq_iqm_fret_err_drop3;               /* 140 */
    volatile csr_stfiq_ifp_start_time_cnt_u stfiq_ifp_start_time_cnt;               /* 144 */
    volatile csr_stfiq_qry_fifo_aful_u stfiq_qry_fifo_aful;                         /* 148 */
    volatile csr_stfiq_qry_fifo_cnt_u stfiq_qry_fifo_cnt;                           /* 14C */
    volatile csr_stfiq_icdq_sqd_bp_u stfiq_icdq_sqd_bp;                             /* 150 */
    volatile csr_stfiq_latency_cfg_u stfiq_latency_cfg;                             /* 154 */
    volatile csr_stfiq_latency_sta_u stfiq_latency_sta;                             /* 158 */
    volatile csr_stfiq_sample_tmr_u stfiq_sample_tmr;                               /* 15C */
    volatile csr_stfiq_earb_roce_rd_pro_type1_u stfiq_earb_roce_rd_pro_type1;       /* 160 */
    volatile csr_stfiq_earb_roce_rd_pro_type2_u stfiq_earb_roce_rd_pro_type2;       /* 164 */
    volatile csr_stfiq_earb_roce_rd_pro_type3_u stfiq_earb_roce_rd_pro_type3;       /* 168 */
    volatile csr_stfiq_quf_pg_cfg_u stfiq_quf_pg_cfg;                               /* 16C */
    volatile csr_stfiq_cntx_timout_wattermark_u stfiq_cntx_timout_wattermark;       /* 170 */
    volatile csr_stfiq_fake_vf_mask_u stfiq_fake_vf_mask;                           /* 174 */
    volatile csr_cmd_pkt_ichannel0_u cmd_pkt_ichannel0;                             /* 178 */
    volatile csr_cmd_pkt_ichannel1_u cmd_pkt_ichannel1;                             /* 17C */
    volatile csr_csr_iqm_cfg_threshold_u csr_iqm_cfg_threshold;                     /* 180 */
    volatile csr_csr_iqm_time_interval_u csr_iqm_time_interval;                     /* 184 */
    volatile csr_csr_iqm_time_out_cnt_u csr_iqm_time_out_cnt;                       /* 188 */
    volatile csr_csr_iqm_time_out_queue0_u csr_iqm_time_out_queue0;                 /* 18C */
    volatile csr_csr_iqm_time_out_queue1_u csr_iqm_time_out_queue1;                 /* 190 */
    volatile csr_csr_iqm_time_out_start_u csr_iqm_time_out_start;                   /* 194 */
} S_qu_stfiq_csr_REGS_TYPE;

/* Declare the struct pointor of the module qu_stfiq_csr */
extern volatile S_qu_stfiq_csr_REGS_TYPE *gopqu_stfiq_csrAllReg;

/* Declare the functions that set the member value */
int iSetSTFIQ_MODE_csr_stfiq_tpmem_timing_ctrl(unsigned int ucsr_stfiq_tpmem_timing_ctrl);
int iSetSTFIQ_MODE_csr_stfiq_spmem_timing_ctrl(unsigned int ucsr_stfiq_spmem_timing_ctrl);
int iSetSTFIQ_MODE_csr_stfiq_tpmem_power_ctrl(unsigned int ucsr_stfiq_tpmem_power_ctrl);
int iSetSTFIQ_MODE_csr_stfiq_spmem_power_ctrl(unsigned int ucsr_stfiq_spmem_power_ctrl);
int iSetSTFIQ_MODE_csr_stfiq_mem_init_start(unsigned int ucsr_stfiq_mem_init_start);
int iSetSTFIQ_MODE_csr_stfiq_mem_ecc_bypass(unsigned int ucsr_stfiq_mem_ecc_bypass);
int iSetSTFIQ_MODE_csr_stfiq_mem_ecc_req(unsigned int ucsr_stfiq_mem_ecc_req);
int iSetSTFIQ_MODE_csr_stfiq_cntx_sf_watchdog_en(unsigned int ucsr_stfiq_cntx_sf_watchdog_en);
int iSetSTFIQ_IMSG_BM_INI_imsg_bm_ini_start(unsigned int uimsg_bm_ini_start);
int iSetSTFIQ_IMSG_BM_INI_imsg_bm_ini_depth(unsigned int uimsg_bm_ini_depth);
int iSetSTFIQ_IMSG_BM_INI_imsg_bm_time_out_interval_cfg(unsigned int uimsg_bm_time_out_interval_cfg);
int iSetSTFIQ_IMSG_BM_TIME_OUT_INTERVAL_imsg_bm_time_out_interval(unsigned int uimsg_bm_time_out_interval);
int iSetSTFIQ_IMSG_BM_INFOR_imsg_bm_ini_busy(unsigned int uimsg_bm_ini_busy);
int iSetSTFIQ_IMSG_BM_INFOR_imsg_bm_ini_done(unsigned int uimsg_bm_ini_done);
int iSetSTFIQ_IMSG_PRO_TYPE_imsg_stf_tmr_pro_typ(unsigned int uimsg_stf_tmr_pro_typ);
int iSetSTFIQ_IMSG_PRO_TYPE_imsg_stl_tmr_pro_typ(unsigned int uimsg_stl_tmr_pro_typ);
int iSetSTFIQ_IMSG_PRO_TYPE_imsg_fcnp_pro_typ(unsigned int uimsg_fcnp_pro_typ);
int iSetSTFIQ_IMSG_PRO_TYPE_imsg_event_pro_typ(unsigned int uimsg_event_pro_typ);
int iSetSTFIQ_IMSG_SOURCE_LIMIT_imsg_msg_pfhid_limit(unsigned int uimsg_msg_pfhid_limit);
int iSetSTFIQ_IMSG_SOURCE_LIMIT_imsg_msg_pfhid_stl_task_tmr_limit(unsigned int uimsg_msg_pfhid_stl_task_tmr_limit);
int iSetSTFIQ_IMSG_DBE_PSH_CPB_imsg_dbe_psh_cpb(unsigned int uimsg_dbe_psh_cpb);
int iSetSTFIQ_IMSG_TMR_SRC_DEFINE0_imsg_tmr_stl_src(unsigned int uimsg_tmr_stl_src);
int iSetSTFIQ_IMSG_TMR_SRC_DEFINE0_imsg_tmr_stf_src(unsigned int uimsg_tmr_stf_src);
int iSetSTFIQ_IMSG_EVENT_SRC_DEFINE1_imsg_tsk_src(unsigned int uimsg_tsk_src);
int iSetSTFIQ_IMSG_EVENT_SRC_DEFINE1_imsg_fcnp_src(unsigned int uimsg_fcnp_src);
int iSetSTFIQ_CLOSE_FQ_LOAD_BALANCE_close_fq_load_balance(unsigned int uclose_fq_load_balance);
int iSetSTFIQ_FQ_QPC_RSP_FIFO_AFUL_stfiq_fq0_qpc_rsp_aful(unsigned int ustfiq_fq0_qpc_rsp_aful);
int iSetSTFIQ_FQ_QPC_RSP_FIFO_AFUL_stfiq_fq1_qpc_rsp_aful(unsigned int ustfiq_fq1_qpc_rsp_aful);
int iSetSTFIQ_FQ_QPC_RSP_FIFO_CNT_stfiq_fq0_qpc_rsp_cnt(unsigned int ustfiq_fq0_qpc_rsp_cnt);
int iSetSTFIQ_FQ_QPC_RSP_FIFO_CNT_stfiq_fq1_qpc_rsp_cnt(unsigned int ustfiq_fq1_qpc_rsp_cnt);
int iSetSTFIQ_RITF_PERX_IO_LAST_NUM_perx_io_last_flag_num(unsigned int uperx_io_last_flag_num);
int iSetSTFIQ_RITF_PERX_IO_FIRST_NUM_perx_io_first_flag_num(unsigned int uperx_io_first_flag_num);
int iSetSTFIQ_RITF_IPSUTX_IO_LAST_NUM_ipsutx_io_last_flag_num(unsigned int uipsutx_io_last_flag_num);
int iSetSTFIQ_RITF_IPSUTX_IO_FIRST_NUM_ipsutx_io_first_flag_num(unsigned int uipsutx_io_first_flag_num);
int iSetSTFIQ_RITF_IO_RSP_NUM_ritf_io_rsp_num(unsigned int uritf_io_rsp_num);
int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_stffq_lb(unsigned int ustfiq_wrr_weight_stffq_lb);
int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_oq_lb(unsigned int ustfiq_wrr_weight_oq_lb);
int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_icdq(unsigned int ustfiq_wrr_weight_icdq);
int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_stlfq_dsp(unsigned int ustfiq_wrr_weight_stlfq_dsp);
int iSetSTFIQ_WRR_WEIGHT_ENQ1_stfiq_wrr_weight_stliq_ret(unsigned int ustfiq_wrr_weight_stliq_ret);
int iSetSTFIQ_FLB_UPDATE_PD_EN_flb_update_pd_en(unsigned int uflb_update_pd_en);
int iSetSTFIQ_FLB_UPDATE_PD_EN_flb_update_epd_en(unsigned int uflb_update_epd_en);
int iSetSTFIQ_ERRPKT_DROP_EN0_errpkt_drop_en0(unsigned int uerrpkt_drop_en0);
int iSetSTFIQ_ERRPKT_DROP_EN1_errpkt_drop_en1(unsigned int uerrpkt_drop_en1);
int iSetSTFIQ_ERRPKT_DROP_EN2_errpkt_drop_en2(unsigned int uerrpkt_drop_en2);
int iSetSTFIQ_ERRPKT_DROP_EN3_errpkt_drop_en3(unsigned int uerrpkt_drop_en3);
int iSetSTFIQ_WRR_WEIGHT_ENQ2_stfiq_wrr_weight_qry(unsigned int ustfiq_wrr_weight_qry);
int iSetSTFIQ_WRR_WEIGHT_ENQ2_stfiq_wrr_weight_enq(unsigned int ustfiq_wrr_weight_enq);
int iSetSTFIQ_IMSG_MSG_FIFO_AF_imsg_dbe_aful(unsigned int uimsg_dbe_aful);
int iSetSTFIQ_IMSG_MSG_FIFO_AF_fq0_timer_aful(unsigned int ufq0_timer_aful);
int iSetSTFIQ_IMSG_MSG_FIFO_AF_fq1_timer_aful(unsigned int ufq1_timer_aful);
int iSetSTFIQ_IMSG_STL_STF_MSG_AF_stlmsg_aful(unsigned int ustlmsg_aful);
int iSetSTFIQ_IMSG_STL_STF_MSG_AF_stfmsg_aful(unsigned int ustfmsg_aful);
int iSetSTFIQ_RITF_FIFO_AFUL0_pe_event_aful(unsigned int upe_event_aful);
int iSetSTFIQ_RITF_FIFO_AFUL0_fcnp_event_aful(unsigned int ufcnp_event_aful);
int iSetSTFIQ_RITF_FIFO_AFUL0_perx_event_aful(unsigned int uperx_event_aful);
int iSetSTFIQ_RITF_FIFO_AFUL0_ipsutx_event_aful(unsigned int uipsutx_event_aful);
int iSetSTFIQ_RITF_FIFO_AFUL1_taskid_order_aful(unsigned int utaskid_order_aful);
int iSetSTFIQ_IARB_FIFO_AFUL0_stor_icdq_infor_aful(unsigned int ustor_icdq_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL0_stor_stffq0_flb_infor_aful(unsigned int ustor_stffq0_flb_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL0_stor_stffq1_flb_infor_aful(unsigned int ustor_stffq1_flb_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL0_stor_oq_olb_infor_aful(unsigned int ustor_oq_olb_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stliq_ret_infor_aful(unsigned int ustor_stliq_ret_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stlfq_dsp_infor_aful(unsigned int ustor_stlfq_dsp_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stffq0_qry_infor_aful(unsigned int ustor_stffq0_qry_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stffq1_qry_infor_aful(unsigned int ustor_stffq1_qry_infor_aful);
int iSetSTFIQ_IARB_FIFO_AFUL2_stor_pd_infor_aful(unsigned int ustor_pd_infor_aful);
int iSetSTFIQ_IMSG_MSG_FIFO_CNT_imsg_dbe_cnt(unsigned int uimsg_dbe_cnt);
int iSetSTFIQ_IMSG_MSG_FIFO_CNT_fq0_timer_cnt(unsigned int ufq0_timer_cnt);
int iSetSTFIQ_IMSG_MSG_FIFO_CNT_fq1_timer_cnt(unsigned int ufq1_timer_cnt);
int iSetSTFIQ_IMSG_STL_STF_MSG_CNT_stlmsg_cnt(unsigned int ustlmsg_cnt);
int iSetSTFIQ_IMSG_STL_STF_MSG_CNT_stfmsg_cnt0(unsigned int ustfmsg_cnt0);
int iSetSTFIQ_IMSG_STL_STF_MSG_CNT_stfmsg_cnt1(unsigned int ustfmsg_cnt1);
int iSetSTFIQ_RITF_FIFO_CNT0_pe_event_cnt(unsigned int upe_event_cnt);
int iSetSTFIQ_RITF_FIFO_CNT0_fcnp_event_cnt(unsigned int ufcnp_event_cnt);
int iSetSTFIQ_RITF_FIFO_CNT0_perx_event_cnt(unsigned int uperx_event_cnt);
int iSetSTFIQ_RITF_FIFO_CNT0_ipsutx_event_cnt(unsigned int uipsutx_event_cnt);
int iSetSTFIQ_RITF_FIFO_CNT1_taskid_order_cnt(unsigned int utaskid_order_cnt);
int iSetSTFIQ_IARB_FIFO_CNT0_stor_icdq_infor_cnt(unsigned int ustor_icdq_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT0_stor_stffq0_flb_infor_cnt(unsigned int ustor_stffq0_flb_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT0_stor_stffq1_flb_infor_cnt(unsigned int ustor_stffq1_flb_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT0_stor_oq_olb_infor_cnt(unsigned int ustor_oq_olb_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT1_stor_stliq_ret_infor_cnt(unsigned int ustor_stliq_ret_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT1_stor_stlfq_dsp_infor_cnt(unsigned int ustor_stlfq_dsp_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT1_stor_stffq0_qry_infor_cnt(unsigned int ustor_stffq0_qry_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT1_stor_stffq1_qry_infor_cnt(unsigned int ustor_stffq1_qry_infor_cnt);
int iSetSTFIQ_IARB_FIFO_CNT2_stor_pd_infor_cnt(unsigned int ustor_pd_infor_cnt);
int iSetSTFIQ_MEM_INIT_DONE_mem_init_done(unsigned int umem_init_done);
int iSetSTFIQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index);
int iSetSTFIQ_INT_VECTOR_enable(unsigned int uenable);
int iSetSTFIQ_INT_VECTOR_int_issue(unsigned int uint_issue);
int iSetSTFIQ_INT_int_data(unsigned int uint_data);
int iSetSTFIQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro);
int iSetSTFIQ_INT_EN_int_en(unsigned int uint_en);
int iSetSTFIQ_INT_EN_program_csr_id(unsigned int uprogram_csr_id);
int iSetSTFIQ_INT0_STICKY_imsg_bm_time_out_rpt(unsigned int uimsg_bm_time_out_rpt);
int iSetSTFIQ_INT0_STICKY_int_insrt0(unsigned int uint_insrt0);
int iSetSTFIQ_INT0_STICKY_stfiq_int0_sticky(unsigned int ustfiq_int0_sticky);
int iSetSTFIQ_INT1_STICKY_stfiq_fifo_overflow0(unsigned int ustfiq_fifo_overflow0);
int iSetSTFIQ_INT1_STICKY_int_insrt10(unsigned int uint_insrt10);
int iSetSTFIQ_INT1_STICKY_stfiq_int1_sticky0(unsigned int ustfiq_int1_sticky0);
int iSetSTFIQ_INT2_STICKY_stfiq_fifo_underflow0(unsigned int ustfiq_fifo_underflow0);
int iSetSTFIQ_INT2_STICKY_int_insrt20(unsigned int uint_insrt20);
int iSetSTFIQ_INT2_STICKY_stfiq_int2_sticky0(unsigned int ustfiq_int2_sticky0);
int iSetSTFIQ_INT3_STICKY_stfiq_ram_ecc_cerr(unsigned int ustfiq_ram_ecc_cerr);
int iSetSTFIQ_INT3_STICKY_int_insrt3(unsigned int uint_insrt3);
int iSetSTFIQ_INT3_STICKY_stfiq_int3_sticky(unsigned int ustfiq_int3_sticky);
int iSetSTFIQ_INT4_STICKY_stfiq_ram_ecc_ucerr(unsigned int ustfiq_ram_ecc_ucerr);
int iSetSTFIQ_INT4_STICKY_int_insrt4(unsigned int uint_insrt4);
int iSetSTFIQ_INT4_STICKY_stfiq_int4_sticky(unsigned int ustfiq_int4_sticky);
int iSetSTFIQ_INDRECT_CTRL_csr_stfiq_indrect_ctrl(unsigned int ucsr_stfiq_indrect_ctrl);
int iSetSTFIQ_INDRECT_TIMEOUT_csr_stfiq_indrect_timeout(unsigned int ucsr_stfiq_indrect_timeout);
int iSetSTFIQ_INDRECT_DAT0_csr_stfiq_indrect_data0(unsigned int ucsr_stfiq_indrect_data0);
int iSetSTFIQ_INDRECT_DAT1_csr_stfiq_indrect_data1(unsigned int ucsr_stfiq_indrect_data1);
int iSetSTFIQ_INDRECT_DAT2_csr_stfiq_indrect_data2(unsigned int ucsr_stfiq_indrect_data2);
int iSetSTFIQ_INDRECT_DAT3_csr_stfiq_indrect_data3(unsigned int ucsr_stfiq_indrect_data3);
int iSetSTFIQ_INDRECT_DAT4_csr_stfiq_indrect_data4(unsigned int ucsr_stfiq_indrect_data4);
int iSetSTFIQ_INDRECT_DAT5_csr_stfiq_indrect_data5(unsigned int ucsr_stfiq_indrect_data5);
int iSetSTFIQ_INDRECT_DAT6_csr_stfiq_indrect_data6(unsigned int ucsr_stfiq_indrect_data6);
int iSetSTFIQ_PREFETCH_REQ_CNT0_stfiq_csr_prefetch_req_inc0(unsigned int ustfiq_csr_prefetch_req_inc0);
int iSetSTFIQ_PREFETCH_REQ_CNT1_stfiq_csr_prefetch_req_inc1(unsigned int ustfiq_csr_prefetch_req_inc1);
int iSetSTFIQ_PREFETCH_RSP_CNT0_stfiq_csr_prefetch_rsp_cnt0(unsigned int ustfiq_csr_prefetch_rsp_cnt0);
int iSetSTFIQ_PREFETCH_RSP_CNT1_stfiq_csr_prefetch_rsp_cnt1(unsigned int ustfiq_csr_prefetch_rsp_cnt1);
int iSetSTFIQ_CNT_DB_stfiq_csr_cnt_db_inc(unsigned int ustfiq_csr_cnt_db_inc);
int iSetSTFIQ_CNT_TMR_stfiq_csr_cnt_tmr_inc(unsigned int ustfiq_csr_cnt_tmr_inc);
int iSetSTFIQ_CNT_TSK_stfiq_csr_cnt_tsk_inc(unsigned int ustfiq_csr_cnt_tsk_inc);
int iSetSTFIQ_CNT_FCNP_stfiq_csr_cnt_fcnp_inc(unsigned int ustfiq_csr_cnt_fcnp_inc);
int iSetSTFIQ_CNT_MSG_SCHEDULE_stfiq_csr_cnt_msg_schedule_inc(unsigned int ustfiq_csr_cnt_msg_schedule_inc);
int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE0_csr_stfiq_roce_rd_pro_type0(unsigned int ucsr_stfiq_roce_rd_pro_type0);
int iSetSTFIQ_IQM_FRET_ERR_DROP0_fret_err_drop_en0(unsigned int ufret_err_drop_en0);
int iSetSTFIQ_IQM_FRET_ERR_DROP1_fret_err_drop_en1(unsigned int ufret_err_drop_en1);
int iSetSTFIQ_IQM_FRET_ERR_DROP2_fret_err_drop_en2(unsigned int ufret_err_drop_en2);
int iSetSTFIQ_IQM_FRET_ERR_DROP3_fret_err_drop_en3(unsigned int ufret_err_drop_en3);
int iSetSTFIQ_IFP_START_TIME_CNT_csr_stfiq_ifp_start_time_cnt(unsigned int ucsr_stfiq_ifp_start_time_cnt);
int iSetSTFIQ_QRY_FIFO_AFUL_qry_eop_gain_fifo_af_th(unsigned int uqry_eop_gain_fifo_af_th);
int iSetSTFIQ_QRY_FIFO_AFUL_cntxsf_fifo_af_th(unsigned int ucntxsf_fifo_af_th);
int iSetSTFIQ_QRY_FIFO_CNT_qry_eop_gain_fifo_fill(unsigned int uqry_eop_gain_fifo_fill);
int iSetSTFIQ_QRY_FIFO_CNT_cntxsf_fifo_fill(unsigned int ucntxsf_fifo_fill);
int iSetSTFIQ_ICDQ_SQD_BP_csr_iqm_cfg_sqd_bp(unsigned int ucsr_iqm_cfg_sqd_bp);
int iSetSTFIQ_LATENCY_CFG_csr_stfiq_sample_mode(unsigned int ucsr_stfiq_sample_mode);
int iSetSTFIQ_LATENCY_CFG_csr_stfiq_spec_port_en(unsigned int ucsr_stfiq_spec_port_en);
int iSetSTFIQ_LATENCY_CFG_csr_stfiq_done_clr(unsigned int ucsr_stfiq_done_clr);
int iSetSTFIQ_LATENCY_CFG_csr_stfiq_spec_port_num(unsigned int ucsr_stfiq_spec_port_num);
int iSetSTFIQ_LATENCY_CFG_csr_stfiq_spec_pptr_typ(unsigned int ucsr_stfiq_spec_pptr_typ);
int iSetSTFIQ_LATENCY_STA_stfiq_csr_sample_done(unsigned int ustfiq_csr_sample_done);
int iSetSTFIQ_SAMPLE_TMR_stfiq_csr_sample_tmr(unsigned int ustfiq_csr_sample_tmr);
int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE1_csr_stfiq_roce_rd_pro_type1(unsigned int ucsr_stfiq_roce_rd_pro_type1);
int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE2_csr_stfiq_roce_rd_pro_type2(unsigned int ucsr_stfiq_roce_rd_pro_type2);
int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE3_csr_stfiq_roce_rd_pro_type3(unsigned int ucsr_stfiq_roce_rd_pro_type3);
int iSetSTFIQ_QUF_PG_CFG_csr_stfiq_quf_pg_cfg(unsigned int ucsr_stfiq_quf_pg_cfg);
int iSetSTFIQ_CNTX_TIMOUT_WATTERMARK_csr_cntx_sf_timeout_watermark(unsigned int ucsr_cntx_sf_timeout_watermark);
int iSetSTFIQ_FAKE_VF_MASK_csr_stfiq_fake_vf_mask(unsigned int ucsr_stfiq_fake_vf_mask);
int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel0(unsigned int ucmd_pkt_ichannel0);
int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel1(unsigned int ucmd_pkt_ichannel1);
int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel2(unsigned int ucmd_pkt_ichannel2);
int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel3(unsigned int ucmd_pkt_ichannel3);
int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel4(unsigned int ucmd_pkt_ichannel4);
int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel5(unsigned int ucmd_pkt_ichannel5);
int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel6(unsigned int ucmd_pkt_ichannel6);
int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel7(unsigned int ucmd_pkt_ichannel7);
int iSetCSR_IQM_CFG_THRESHOLD_csr_iqm_cfg_threshold0(unsigned int ucsr_iqm_cfg_threshold0);
int iSetCSR_IQM_CFG_THRESHOLD_csr_iqm_cfg_threshold1(unsigned int ucsr_iqm_cfg_threshold1);
int iSetCSR_IQM_TIME_INTERVAL_csr_iqm_time_interval(unsigned int ucsr_iqm_time_interval);
int iSetCSR_IQM_TIME_OUT_CNT_csr_iqm_time_out_cnt(unsigned int ucsr_iqm_time_out_cnt);
int iSetCSR_IQM_TIME_OUT_QUEUE0_csr_iqm_time_out_queue0(unsigned int ucsr_iqm_time_out_queue0);
int iSetCSR_IQM_TIME_OUT_QUEUE1_csr_iqm_time_out_queue1(unsigned int ucsr_iqm_time_out_queue1);
int iSetCSR_IQM_TIME_OUT_START_csr_iqm_time_out_start(unsigned int ucsr_iqm_time_out_start);


#endif // STFIQ_C_UNION_DEFINE_H
